This invention relates to an insulated-gate field-effect transistor (IGFET) of vertical channel design such for example as a metal-oxide-semiconductor field-effect transistor (MOSFET), and to a metal of fabricating the same.
A type of IGFET with a large current-carrying capacity, the MOSFET finds use as, for example, a switch in electric circuits. A typical conventional MOSFET has a source electrode in ohmic contact with both source region and body (base) region. As a consequence, between the drain and source electrodes, the current path exists not only through the channel in the body region but, additionally, through a parasitic diode (sometimes referred to as a body diode or built-in diode) created by reason of the pn junction between the drain and body regions. If this known MOSFET has a channel of n-type semiconductor material (nMOSFET), the parasitic diode is reverse biased when the drain electrode is higher in potential than the source electrode, blocking the current flow therethrough. However, under the requirements of the electric circuit incorporating the MOSFET, the drain electrode may be less in potential than the source electrode. In that case the parasitic diode will be forward biased, permitting a current flow therethrough. This feature of the MOSFET is of particularly utility when it is used as a switch in an inverter (DC-to-AC converter) circuit, because then a regenerative current can be made to flow through the parasitic diode.
However, there also exist other circuits that require the prevention of current flow through the parasitic diode. This requirement has so far been met by connecting the MOSFET in series with an external diode having a polarity (orientation) opposite to that of the parasitic diode. The external diode is in fact a reverse blocking diode, preventing a current flow through the MOSFET when the drain electrode is less in potential than the source electrode. A fabrication of this external diode on one and the same semiconductor substrate as the MOSFET is objectionable by reasons of the unnecessarily large size substrate required and the higher manufacturing cost of the resulting composite integrated device. A manufacture of the MOSFET and the external diode on separate semiconductor substrates is also undesirable for the larger size and expensiveness of the two devices combined. Moreover, power loss will inevitably occur as a result of the flow of the same current through the external diode as through the MOSFET. The connection of the external diode in series with the MOSFET brings about the additional inconvenience that the MOSFET current is uncontrollable when the drain electrode is less in potential than the source electrode, that is, when a reverse voltage is being impressed to the MOSFET.
With a view to defeating the problems arising from use of the external diode in combination with the MOSFET of the noted prior art construction, Japanese Unexamined Patent Publication No. 7-15009 suggests an advanced planar MOSFET where the source electrode is in schottky contact with the body region. FIG. 1 is a sectional illustration of this advanced prior art planar MOSFET, and FIG. 2 its equivalent circuit diagram.
Referring more specifically to FIG. 1, the prior art planar MOSFET comprises a semiconducting silicon substrate 1′, a drain electrode 2′, a source electrode 3′, a gate electrode 4′, and a gate insulator film 5′. The semiconductor substrate 1′ comprises a first drain region 6′ of n+-type semiconductor material with a high impurity concentration, a second drain (or drift) region 7′ of n−-type semiconductor material with a low impurity concentration, a first body (or base) region 8′ of p-type semiconductor material with a high impurity concentration, a second body (or base) region 9′ of p−-type semiconductor material with a low impurity concentration, and a source region 10′ of n+-type semiconductor material with a high impurity concentration. The substrate 1′ has a pair of opposite major surfaces 1a′ and 1b′. The drain electrode 2′ is formed on the second major surface 1b′ in ohmic contact with the first drain region 6′. The source electrode 3′ is formed on the first major surface 1a′ in ohmic contact with the n+-type source region 10′ and schottky contact with the p−-type second body region 9′. Also formed on the first major surface 1a′, the gate electrode 4′ is opposed to both p-type first body region 8′ and p−-type second body region 9′ via the gate insulator film 5′.
In the prior art planar MOSFET constructed as in FIG. 1, upon application of such a voltage between drain electrode 2′ and source electrode 3′ as to make the former higher in potential than the latter, and of a voltage sufficiently high to turn on the MOSFET between gate electrode 4′ and source electrode 3′, then an n-type channel 13′ will be created in the surfaces of the first body region 8′ and second body region 9′, as indicated by the dashed lines in FIG. 1. Then drain current will flow along the path sequentially comprising the drain electrode 2′, first drain region 6′, second drain region 7′, channel 13′, n+-type source region 10′, and source electrode 3′.
The circuit diagram of FIG. 2, equivalently depicting how the prior art planar MOSFET of FIG. 1 is electrically circuited, indicates that it comprises a first and a second pn-junction diode D1 and D2 and a schottky-barrier diode D3 in addition to an FET switch Q1. The first pn-junction diode D1 is a parasitic (built-in) diode based upon the pn junction between n-type second drain region 7′ and p-type first body region 8′. The second pn-junction diode D2 is another such diode based upon the pn junction between p−-type second body region 9′ and n+-type source region 10′. The schottky-barrier diode D3 is based upon the schottky junction between source electrode 3′ and p−-type second body region 9′. Polarized to be reverse biased when the drain electrode 2′ is higher in potential than the source electrode 3′, the first pn-junction diode D1 is connected in inverse parallel with the FET switch Q1. The second pn-junction diode D2 has a polarity opposite to that of the first pn-junction diode D1 and is connected in series therewith. In the noted more conventional MOSFET having no schottky-barrier diode D3, this part of the device is short-circuited, so that the second pn-junction diode D2 has no function whatsoever and does not appear in the equivalent circuit. The schottky-barrier diode D3 has a polarity opposite to that of the first pn-junction diode D1 and is connected in series with the first pn-junction diode D1 and in parallel with the second pn-junction diode D2.
Such being the construction of the prior art planar MOSFET shown in FIGS. 1 and 2, the first pn-junction diode D1 will be reverse biased, and the schottky-barrier diode D3 forward biased, when the drain electrode 2′ is higher in potential than the source electrode 3′. Thus the device operates just like the more conventional MOSFET set forth above. Conversely, when the drain electrode 2′ is less in potential than the source electrode 3′, both schottky-barrier diode D3 and second pn-junction diode D2 will be reverse biased, blocking reverse current flow through paths other than the channel.
However, the prior art planar MOSFET of FIG. 1 possesses the following shortcomings:
1. The p−-type second body region 9′ becomes higher in potential than the n+-type source region 10′ because of the potential difference of approximately 0.2 volt due to the schottky barrier between source electrode 3′ and p−-type second body region 9′. For this reason, when the drain electrode 2′ is higher in potential than the source electrode 3′, there occurs an inflow or injection of electrons from n+-type source region 10′ to p−-type second body region 9′. The current flowing between drain electrode 2′ and source electrode 3′ by reason of this electron injection is a leak current. The antivoltage strength between the drain and source of any device of this type is customarily assessed in the semiconductor industry in terms of the magnitude of leak current: The more leak current, the lower is the rating of the drain-source antivoltage strength of the device.
2. The leak current now under consideration is controllable by lowering the impurity concentration of that part of the n+-type source region 10′ which adjoins the second body region 9′. Being formed by impurity diffusion, the n+-type source region 10′ grows less in impurity concentration from the first major surface 1a′ toward the second major surface 1b′ of the substrate 1′. It might be contemplated to lower the impurity concentration of the required part of the n+-type source region 10′ by making this region 10′ deeper. The deepening of the n+-type source region 10′ would necessitate that of the two body regions 8′ and 9′ as well. With the body regions 8′ and 9′ and source region 10′ thus deepened, more lateral diffusions of both p- and n-type impurities would take place, with the result that these regions would occupy greater surface areas of the chip. Experiment has proved that the chip surface of the substrate 1′ becomes as large as 1.7 times that of the known planar MOSFET having no schottky-barrier diode, making it impossible to make the device smaller in size. Also, by deepening the body regions 8′ and 9′ and source region 10′, the maximum depth of the second drain region 7′ (i.e., the distance between its surface exposed at the first major surface 1a′ of the substrate 1′ and its boundary with the n+-type first drain region 6′) would be 1.5 times that in the prior art planar MOSFET having no schottky-barrier diode. As a result, the on-resistance between the drain electrode 2′ and source electrode 3′ of the prior art planar MOSFET having the schottky-barrier diode as in FIG. 1 would become as high as, say, approximately four times that of the prior art planar MOSFET having no schottky-barrier diode. For this drawback the prior art planar MOSFET of FIG. 1 has not been placed on the market.